CMOS integrated circuits having a very large integration of CMOS field effect transistors (FET) have the advantage of consuming little power in quiescent state. However, compared to bipolar transistors, CMOS are disadvantageous in having lower breakdown voltages (BVDSS), which is a function of device topology and manufacturing process. With an industry standard 1.5-micron CMOS process, BVDSS is typically about 10V nominal. With typical operational voltages of 0-5V, the relatively low breakdown voltages are not a problem. However, when a CMOS circuit interfaces with an external device, higher voltages which exceed the breakdown voltage of the CMOS device are often encountered. It is thus desirable to provide a CMOS circuit that can withstand higher voltages without having to modify well established fabrication processes.
Another problem in CMOS devices is its high susceptibility to electrostatic discharge (ESD). This is due to it being a very high impedance device, whereby electrostatic charges often find a lower impedance path through rupturing the device. To provide improved reliability, it is thus desirable to provide better ESD protection.